1. Field of the Invention
The invention relates to a switching converting circuit and a controller thereof. More particularly, the invention relates to a de-glitch switching converting circuit and a controller thereof.
2. Description of Related Art
For power supplies, switching converting circuits are mainstream products in the current market due to superior properties of high converting efficiency, small size, and low power consumption while no load. However, switching converting circuits have the disadvantages of complex circuit design, large ripples, and large electromagnetic interference (EMI). In the current market, common switching converting circuits mainly have two types of control methods. One is pulse width modulated (PWM), and the other is pulse frequency modulated (PFM). Due to constant frequency in PWM technology, EMI is more easily filtered, and the capability of de-glitch is stronger. However, the disadvantages of switching converting circuits with PWM technology are low converting efficiency and slow transient response while light load. On the contrary, PFM technology has advantages of high converting efficiency and fast transient response. However, EMI is not easily filtered, and the capability of de-glitch is weak in switching converting circuits with PFM technology.
FIG. 1 is a schematic circuit diagram of a conventional DC-to-DC buck converting circuit with PFM technology.
Referring to FIG. 1, the DC-to-DC buck converting circuit includes a switch SW, a synchronous diode D, an inductor L, an output capacitor C, a voltage detecting circuit which composed of resistors R1 and R2, and a controller 10. The voltage detecting circuit detects an output voltage VOUT of the DC-to-DC buck converting circuit and thereby generates a voltage feedback signal VFB. The controller 10 includes a comparator 12, a constant pulse width controller 22, and a driver 32. The comparator 12 receives the voltage feedback signal VFB and a reference signal Vref and triggers the constant pulse width controller 22 to generate a constant pulse width signal with constant width to the driver 32 while the level of the voltage feedback signal VFB is lower than that of the reference signal Vref. The driver 32 generates a control signal Sc to switch the switch SW according to the pulse width signal of the constant pulse width controller 22 and thereby controls an amount of the power which is transmitted from an input voltage VIN to the output end, such that the output voltage VOUT is stabilized about a specific voltage level.
FIG. 2 is a timing diagram of signals of the DC-to-DC buck converting circuit shown in FIG. 1. Referring to FIG. 2, when the level of the voltage feedback signal VFB is reduced to that of the reference signal Vref, the controller 10 generates the control signal Sc with constant pulse width to conduct the switch SW to transmit the power to the output end, such that the output voltage VOUT is increased. The voltage feedback signal VFB has some ripples due to noise interference, such that the controller may erroneously operate and affect the stability of the output voltage VOUT. As shown in FIG. 2, the part of the output voltage VOUT circled by the dotted circle Q is interfered by noises, such that the controller erroneously operates and untimely outputs the control signal Sc, and thereby the maximum of the output voltage VOUT circled by the dotted circle S is obviously higher than that of the output voltage VOUT in other periods.
In order to reduce noise interference, Richtek Technology Corp. discloses an apparatus and a method for noise sensitivity improvement to a switching system in U.S. Pat. No. 7,023,253. FIG. 3 is a schematic circuit diagram of the switching system disclosed in the foregoing patent. Referring to FIG. 3, the controller 10′ includes two amplifiers 14 and 15, a low-pass filter (LPF) 16, a summing circuit 18, a comparator 24, and a constant on-time circuit 31. The amplifier 14 amplifies the feedback signal VFB by a gain K to generate an amplified signal FBF, while the amplifier 15 amplifies the feedback signal VFB by a gain N to generate a signal filtered by the LPF 16 to generate an amplified and filtered signal FBS. The summing circuit 18 combines the signals FBF and FBS to generate an output signal FBX. The comparator 24 compares the output signal FBX and the reference signal Vref and triggers the constant on-time circuit 31 to generate control signals S1 and S2 to respectively control a first switch SW1 and a second switch SW2 while the level of output signal FBX is lower than that of the reference signal Vref. FIG. 4 is a timing diagram of signals of the switching system shown in FIG. 3. Referring to FIG. 4, the level of the amplified signal FBF is increased, such that the level which is located at the wave trough and easily has noises is relatively farther from the wave trough to achieve the objective of reducing noises.
However, in order to filter noises, the LPF 16 provided in the foregoing patent requires a larger capacitor to achieve the objective of filtering. Hence, it is necessary to increase the area of the die to dispose the capacitor for filtering or increase the pins of the chip to externally connect the capacitor for filtering, such that the cost is increased. In addition, for noises with high amplitudes, the circuit may also erroneously operate such that the stability of the output voltage is still affected.